1. Field of the Invention
The present invention relates to a method for fabricating integrated circuits and, more particularly, to improving the peeling issues due to the exposed polysilicon of capacitors after the planarization process.
2. Description of the Prior Art
In general, the fabrication of integrated circuits includes at least four steps with respect to forming polysilicon layers and some steps with respect to forming interconnects. The devices in the substrate should be previously formed.
The first polysilicon layer (poly-1) intends mainly the gate electrodes. It is formed on the substrate and after the devices in the substrate are done. The second polysilicon layer (poly-2) intends mainly the bit lines of integrated circuits. Commonly, they are located over and are perpendicular to the gates. There is at least one dielectric layer formed between two polysilicon layers.
The third polysilicon layer (poly-3), as shown in FIG. 1, usually intends the lower electrodes 102 of capacitors. They are formed on the dielectric layer 101 overhead the second polysilicon layer which is ignored in FIG. 1. Further, the lower electrodes 102 of capacitors directly contact directly to the substrate 100. To increase the storage capacities, different shapes of electrodes have been developed, as for example, a cylinder or a hollow cylinder, etc. A dielectric layer 103 is then formed on the poly-3. The fourth polysilicon layer (poly-4) 104 is subsequently deposited on the dielectric layer 103 to serve as the upper electrodes of the capacitors. According to the steps mentioned above, the capacitors of integrated circuits are then completed.
Before the interconnect metal is fabricated, a dielectric layer 105 should be formed for electric isolation and then planarized to facilitate the fabrication of metal.
Referring to FIG. 2, after the dielectric layer 105 is planarized by chemical mechanical polishing (CMP), the portions, beside the periphery region, of most of the capacitors are easily exposed. In the following steps for forming the first metal level, the glue layer made of Ti will glue on the part of the exposed third and fourth polysilicon layer (102 and 104) of the capacitors. Unfortunately, the short between capacitors and metal levels occurs, moreover, the Ti metal is easily peeled as gluing on the surface of polysilicon. And the peeled Ti particles will obstruct other following steps of the fabrication, for example, the cell defects in the first metal level near the periphery region of the wafer will occur.
For the foregoing reasons, there is a need to develop a method of forming integrated circuits in order to improve the peeling issues mentioned above. Then, the quality of integrated circuits can be increased.